The invention relates generally to timing control circuits and in particular to a timing control circuit providing a wide dynamic range. Timing circuits are used in a number of applications such as pulse width modulation (PWM), voltage controlled oscillators (VCO), etc. FIG. 1 is a schematic diagram of an existing timing circuit 10 used in a PWM application. As known in the art, a PWM signal is a series of pulses. A controllable current source 12 is used to charge a capacitor 14. When the capacitor 14 reaches a certain voltage, established by a reference voltage applied to the inverting terminal of operational amplifier 16, operational amplifier 16 changes states causing a pulse to end.
A drawback to the circuit of FIG. 1 is that it is difficult to provide a large dynamic range. For a given value of capacitor 14, a very large current is needed to generate narrow pulse widths (i.e., rapid charging of capacitor 14). On the other hand, very small current is needed to provide wide pulse widths (i.e., slow charging of capacitor 14). Unfortunately, controlling small currents can be difficult leading to unstable, wide pulse widths.
If capacitor 14 is increased in value to allow larger currents to be used for larger pulse widths, this creates a detriment in generating narrow pulse widths. If capacitance of capacitor 14 is increased, then larger currents are need to generate small pulse widths. Thus, it is difficult to provide a wide dynamic range pulse widths with the existing timing circuit.
An exemplary embodiment of the invention is a timing circuit comprising a controllable current source and a capacitor coupled to the current source. A resistor and a second capacitor are connected in series. The series resistor and second capacitor are connected in parallel with the capacitor. A trigger circuit has a first terminal coupled to the capacitor. The trigger circuit changes states when a voltage at the first terminal exceeds a reference voltage.